The present invention relates to a multi-layer ferrite chip inductor array which is a surface mounted part, and a manufacturing method thereof.
In electronic machines, being small-sized is always demanded in the market, and parts to be used thereto are similarly demanded to be small-sized. Parts such as inductors or capacitors have originally been furnished with leads, and by applying a laminating method, they have been enabled to bake ceramics and metals together, and a monolithic structure furnished with internal conductors has been put in practice. Thereby, it has been possible to make an element itself small-sized, from which lead wires have been cancelled to turn out surface mounted type parts, and which has succeeded in reducing the occupying areas by those parts.
Nowadays, in chip capacitors or chip resistors, the specification of a 1005 shape (length: 1.0 mm, width: 0.5 mm and height: 0.5 mm) is going to be general, and demands for array mounting a plurality of such elements are increasing. On the other hand, the chip inductor has a disadvantageous phase in making small-sized for forming complicated shapes such as coil shaped internal conductors within ferrite elements. Therefore, comparing with capacitors or resistors, the response to small-sizing demands has been delayed. But, such demand is also large in this field, and at present, a 1608 shape (length: 1.6 mm, width: 0.88 mm and height: 0.8 mm) has become general. As to the chip inductor, as a proposal for attempting to realize high characteristics, for example, if providing a structure where a coiling direction of an internal conductor faces toward a vertical direction with respect to terminal electrodes, a self resonance frequency may be heightened (Unexamined Japanese Utility Model Publications 2-44309(U), JP-A-4-93115(U), and Nikkei Electronics, Apr. 5, 1999 (No.740), pp. 181 to 192).
In designing circuits, there often occur cases a plurality of chip inductors have to be mounted on a circuit board, and a space on the board is much occupied, resulting to invite disadvantage for realizing high integration. Therefore, as disclosed in Post-Examined Japanese Patent Publication 62-24923, a chip inductor array was proposed which carried a plurality of internal conductors in a one chip, but the chip inductor array has particular problems such as cross talk or deterioration of insulation resistance which were not found in a single product of the chip inductor. Miniaturization has recently progressed also in the chip inductor array, and demand has raised for arrays of four (4) circuits carried-therein of 3216 shape (length: 3.2 mm , width: 1.6 mm and height: 1.6 mm). Many proposals have been made for solving problems accompanied with matters particular to arrays or miniaturization.
For example, Unexamined Japanese Patent Publications 5-326270, 5-326271 and 5-326272 disclose that, in the chip inductor array, consideration be paid to arrangement of adjacent internal conductors for obtaining higher inductance with a smaller-sized chip. Further, Unexamined Japanese Patent Publications 6-338414, 7-22243, 8-250333 and 8-264320 show methods for improving cross talk which is mutual action between circuits of the chip inductor array in that a straight internal conductor is shaped in coil or a space between adjacent internal conductors or disposal thereof are considered.
As the manufacturing method of the chip inductor array, a lamination method or an extrusion method are known. Unexamined Japanese Patent Publication 8-306541 describes a production method of the chip inductor array by the extrusion method where a plurality of coil shaped conductors are disposed in parallel at the interior of a magnetic core. But the extrusion method is suited to the chip inductor array of relatively large size, and a lamination method is much employed to the chip inductor array of small size.
A general lamination method will be explained with reference to the process chart of FIG. 7.
A 1st process mixes ferrite powder together with a binder and an organic solvent to make a slurry.
A 2nd process coats the slurry on a film such as PET by a doctor blade method and dries it to form a ferrite sheet.
A 3rd process forms through-holes at predetermined positions of the ferrite sheet by a machining work, a laser beam machining or others.
A 4th process carries out a screen process printing of the internal conductor patterns on the ferrite sheets formed with the through-holes, using a conductor paste containing metal powders as silver so as to provide conductor patterns. The through-holes are at this time filled with the conductor paste.
A 5th process laminates the ferrite sheets formed with the internal conductor patterns in a predetermined order. The internal conductor patterns printed on the respective ferrite sheets are then electrically connected with terminal electrodes by the conductors filled in the through-holes and are shaped in coil.
A 6th process heats and presses the laminated ferrite sheets.
A 7th process cuts the heated and pressed laminated ferrite sheets into arbitrary sizes to form chip shapes.
An 8th process heats the chips and removes the binder.
A 9th process bakes and sinters the chips having removed the binder.
A 10th process grinds the above baked chips by a method such as a barrel.
An 11th process forms the terminal electrodes of the predetermined number with the conductor paste such as silver by the screen process printing or roller transcription, and performs the baking treatment thereon, said terminal electrodes being arranged in opposition to the vertical face with respect to the element mounted surface on the chips. The terminal electrode is electrically connected with the terminal electrodes by the conductor extending a starting terminal and an ending terminal of the coil shaped internal conductor.
An 12th process carries out the film treatment on the terminal electrodes by, for example, an electrolytic plating.
Passing through the above processes, the chip inductor carrying the coil shaped internal conductors in the magnetic body is obtained. A plurality of coil shaped internal conductors are housed in the magnetic body to turn out the multi-layer ferrite chip inductor arrays as shown in FIG. 6. Further, Unexamined Japanese Patent Publication 11-26241 shows the chip inductor arrays where the coiling direction of the coil shaped internal conductor is parallel with the mounting surface. In this disclosed chip inductor, the terminal electrode is fabricated with the conductor sheet, and the conductor between the respective terminals is removed for insulation.
However, for forming the multi-layer ferrite chip inductor array of the 2010 Type (length: 2.0 mm and width: 1.0 mm) where the miniaturization has been advanced, there are problems that the only prior art cannot solve as follows.
First, the conventional terminal electrode was formed by baking the coil shaped internal conductor and the ferrite layer, performing the screen process printing or the roller transcription, and further baking. In this case, since the printing or the transcription is directly done to the ferrite sintered body, it is difficult to set the printing or transcribing precision within predetermined designing values, and since the smaller the shape of the chip inductor array, the smaller the space between the adjacent terminal electrodes, the formation is more difficult. When fabricating the terminal electrode by the conductor sheet, a further process is required for removing conductors between the electrodes.
Second, since the shape of the chip inductor array element is small, when obtaining the inductance of the equal size to the conventional one, if other designs are the same, the spaces between circuits of the coil shaped internal conductors are inevitably narrow. Then, cross talk between circuits is large and is a big obstacle to miniaturization of shapes.
Third, the internal conductors occupying the chip inductor array element and the volume rate of the through-holes are relatively large, so that non-uniform stress is caused in the ferrite structure having the conventional structure of the elements. By effecting stress, the permeability p of the ferrite sintered body is largely varied. In the laminated inductor elements, residual stress occurs by simultaneously baking the internal conductors composed of the electrically conductive material containing silver or terminal electrodes and the ferrite layer, resulting to invite lowering of an apparent xcexc. This xcexc lowering is eased by heat shock when soldering products on the circuit board, and becomes an unstable factor of a characteristic such as fluctuation of impedance. When the element shape is small, the volume rate of the conductor occupying the element increases, and this problem is serious.
Fourth, in parts based on a premise of soldering as the chip inductor array, the electrolytic plating is necessary for making the soldering easy. However, an interface between the conductor containing such as silver and the ferrite layer is easy to generate the residual stress and often causes partial peeling, and so the plating liquid easily goes into this interface. In particular, if it penetrates until the layer of the coil shaped internal conductor, the characteristic is largely changed. As to the printing pattern of the conductor, a limit exists in making lines narrow, and taking the electric resistance into consideration, a width of about 60 xcexcm is a limit of the designing value, and therefore, the smaller the element shape, the more inevitably increased the volume rate of the conductor occupying the element, and the residual stress generated around the interface becomes large. Thus, if the element shape is small, the peeling easily occurs at the interface between the conductor and the ferrite layer, and the plating liquid easily goes into the interior of the element.
Fifth, since the chip inductor array carries the plurality of internal conductors therein, differently from the chip inductor, it has a problem of deterioration of insulating resistance. When the element shape is small, since the space between the circuits of the internal conductors is still narrower, this problem is more serious.
The invention has been realized for solving problems involved with the prior art. Accordingly, the problem that the invention is to solve is to provide the small sized multi-layer ferrite chip inductor array of highly sizing precision and high characteristics as well as a production method thereof. More particularly, the terminal electrode is fabricated with high precision, enabling to check influences by stress of the ferrite layer and by the plating treatment, with less cross talk, high self resonance frequency, little deterioration of insulating resistance.
The above mentioned problems can be solved by the structure as follows.
A multi-layer ferrite chip inductor array, wherein an element main body is composed by laminating a ferrite layer and a conductor layer in such a manner that the laminated face thereof is vertical with an element mounting surface, a plurality of coil shaped internal conductors are furnished within the element main body, the coiling direction of said coil shaped internal conductor being parallel with the element mounting surface, and both terminals of said coil shaped internal conductors are electrically connected with terminal electrodes by means of conductors filled in through-holes.
The multi-layer ferrite chip inductor array as set forth in the above, wherein the terminal electrode comprises an electric conductor containing glass frit 10 wt % to 30 wt %.
A method for making multi-layer ferrite chip inductor arrays, comprises a step of forming ferrite sheets containing ferrite material; a step of forming a plurality of through-holes at predetermined positions of the ferrite sheets; a printing step of forming a plurality of coil shaped internal conductors with a conductor material and conductor patterns of terminal electrodes with the same in the ferrite sheets formed with the through-holes, and filling the conductor materials in the through-holes; and a step of laminating the ferrite sheets after the printing step in such a manner that the laminated layer is vertical with respect to the element mounting surface, and obtaining the laminated bodies formed with a plurality coil shaped inside conductors coiling toward a parallel direction with the element mounting face, the coiling direction of said coil shaped internal conductor being parallel with the element mounting surface.
The method for making multi-layer ferrite chip inductor arrays as set forth in the above, wherein the conductor pattern of the terminal conductor is, prior to the baking step, formed in the ferrite sheet by a screen process printing.
The method for making multi-layer ferrite chip inductor array as set forth in the above, wherein both terminals of said coil shaped internal conductors are electrically connected with terminal electrodes by means of conductors filled in through-holes.
The method for making multi-layer ferrite chip inductor array as set forth in the above, wherein the conductor pattern of the terminal electrode is printed with the electric conductor material containing glass frit 10 wt % to 30 wt %.